Analysis and Design of Networks-on-Chip Under High Process Variation by Rabab Ezz-Eldin Magdy Ali El-Moursy & Hesham F. A. Hamed

Author:Rabab Ezz-Eldin, Magdy Ali El-Moursy & Hesham F. A. Hamed
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

4.4.1.2 Statistical Static Timing Analysis

SSTA is used to model the process variation parameters as random variables with known probability distribution. Therefore, SSTA technique propagates the delay distribution instead of deterministic delay values to determine the probability distribution of the circuit performance [20]. The gate/interconnect delays which are modeled as probability distribution functions (PDFs) or cumulative distribution functions (CDFs) with complex correlations and parametric yields can be predicted [21]. PDF and CDF are shown in Fig. 4.8. SSTA technique is applicable for large circuits since it has the ability to determine the delay distribution in only one timing run. On the other hand, Monte Carlo analysis requires a large number of iterations to determine the delay distribution.

Fig. 4.8The probability distribution function (PDF) and cumulative distribution function (CDF)

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